
/*
**************************************************************************************************************
File:         controller.sv
Description:  Functions as a partial controller - based on inputs, sends signals to interface
Author     :  Katerina Gleeson
**************************************************************************************************************
*/
`include "package.sv"


//import package::*;

//module controller(input CK, ADDR);
module controller(DDR_bus IF, input OP, input [LOGICAL_ADDR_WIDTH-1:0] ADDR);
wire [DATA_WIDTH-1:0] data;
logic [COL_WIDTH-1:0] column;   //7bits 6:0
logic [ROW_WIDTH-1:0] row;      //7bits 13:7 
logic [BANK_ADDR_WIDTH-1:0] bank;
//DDR_bus IF(CK);   //need to use interface

always_ff @(posedge IF.CK) begin   //two high signals would be error
		if(OP)
		  write(ADDR,1);  
end

task write(input [ADDR_WIDTH-1:0] addr,input [DATA_WIDTH-1:0] data);	  
	//IF.ENUM.WR <= HIGH;
	row = ADDR[LOGICAL_ADDR_WIDTH-1:ROW_END];
	bank = ADDR[ROW_END-1:BANK_END];
	column = ADDR[BANK_END-1:0];
	
	
	IF.activate(bank,row);
endtask	
	

endmodule